Booster circuits for reducing latency

ABSTRACT

A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored charge also reduces the charge drawn from the supply during the output transition.

FIELD OF THE INVENTION

Aspects of the present invention relate to circuit techniques forimproving latency and power consumption of digital circuits. Oneparticular aspect of the present invention relates to booster circuitsthat operate in parallel with other digital circuits to decrease latencyand reduce power consumption.

BACKGROUND

Digital circuits may contain millions of devices on a single integratedcircuit. The devices are generally very small to increase speed, reduceenergy consumption and reduce the total area of an integrated circuit.Sometimes, an internally generated signal has to drive a very largeexternal load as quickly as possible, such as when an internal signalhas to drive an input/output pad of the integrated circuit. The internalsignal is generally provided by a very small device that cannot drive alarge load without incurring substantial delays due to the limited drivecurrent available for charging/discharging the capacitive load.

The best performance in terms of minimum delay when an internal signalhas to drive a large load may generally be achieved by using a chain ofinverters, where each inverter is proportioned to the preceding inverterby an amount equal to the ratio of the final load divided by the inputload (C_(L)/C_(in)), otherwise commonly known as the electrical step-up,and this ratio is taken to the root power of the number of stages usedin the chain. The number of stages in the chain is generally chosen suchthat this result is greater than e (about 2.7) but less than e² (about7.3).

In some circuits, such as a pipeline stage of a processor, use ofoptimally sized inverters may not be sufficient to meet timingconstraints. This may be true when the pipeline stage is having troublemeeting timing constraints. Generally, latency is the time delay fromwhen an input of a device changes state to when the output of the devicechanges state. Latency is generally measured from the 50% point of theinput signal transition which caused the output to change, to the 50%point of output signal transition. Thus, what is needed is a circuitthat boosts performance of logic gates with respect to latency and alsoreduces power consumed by the logic gates and/or area consumed by thelogic gates.

SUMMARY

One aspect of the present invention involves a booster circuit fordecreasing latency of a logic gate. The circuit includes an input nodeto receive a logic state transition, a switch element that changes statein response to the logic state transition and a node that has a storedcharge. The node is configured to transfer the stored charge through theswitch element to the output node in response to the logic statetransition. The transfer of stored charge is used to reduce the nominallatency of the logic gate.

Another aspect of the present invention involves a method for reducinglatency of a logic gate. The method involves coupling a booster circuitwith a charge sharing mechanism from the input of the logic gate to theoutput of the logic gate. The method further involves receiving a logicstate transition on the input node and transferring a charge from thecharge sharing mechanism to the output node in response to the logicstate transition. Finally, the method involves decreasing the latency ofthe logic gate through the charge shared.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a technique for minimizing overall delay of a string ofinverters.

FIG. 2 depicts a full booster amplifier circuit of one embodiment of thepresent invention.

FIG. 3 depicts a pull-up booster circuit operating in parallel with twoseries inverters.

FIG. 4 depicts a test setup for three driver configurations modeled inHspice; a driver string having two series inverters and booster circuitper driver, a driver string having two series inverters per driver and adriver string having three series inverters per driver.

FIG. 5 depicts the total charge used by each driver depicted in FIG. 4as a function of total step-up.

FIG. 6 depicts the total transistor width for each driver of FIG. 4 as afunction of total step-up.

FIG. 7 depicts the latency in picoseconds of the driver circuits of FIG.4 as a function of total step-up.

FIG. 8 depicts the latency of the driver circuits of FIG. 4 over abroader range of total step-up.

FIG. 9 depicts the logic switching behavior of an inverter circuit witha booster versus a standard inverter without a booster.

FIG. 10 depicts a full booster circuit for the pull-up and pull-downportion of a two-input AND function.

FIG. 11 depicts the latency of the boosted AND function of FIG. 10 as afunction of total step-up.

FIG. 12 depicts a circuit diagram of a full booster latch.

FIG. 13 depicts a circuit diagram of a simple latch with a pull-upbooster connected in parallel.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

One aspect of the present invention involves circuits for reducinglatency on a logic path while simultaneously saving power when comparedto conventional implementations such as depicted in FIG. 1. Oneembodiment of the present invention utilizes a family of logic circuitsthat digitally evaluates a logic expression (boost circuitry), but whichmay be unable to drive its output to the full logic level. Thesecircuits may be operated in parallel or alongside conventional logicgates or state holding elements that evaluate the same logic expressionto reduce latency and power consumption.

The boost circuitry generally exploits the voltage potential on nodes insuccessive stages of the circuitry where one node is an output, the nodepotentials are opposite of each other, and the nodes want to take on thepotential of the other node when a transition on the output node occurs.By effectively tying the two nodes together, each node may be quicklydriven toward the other by sharing charge and without initiallyrequiring significant charge drawn from the supply. Conventional logicgates operating in parallel with the boost circuitry may complete thetransition by driving the output node to its full digital value. Thus,boost circuitry conforming to aspects of the present invention, may beused in combination with digital circuits to reduce latency and powerconsumption.

FIG. 2 depicts a full amplifier booster circuit. The booster circuit maybe decomposed into a pull-up booster and a pull-down booster. P-channeltransistor PR, n-channel transistor NI and p-channel transistor PU mayoperate as a pull-up booster circuit. N-channel transistor NR, p-channeltransistor PI and n-channel transistor ND may operate as a pull-downbooster. The circuit causes an output transition in response to an inputtransition to occur with less latency by helping the output reach the50% point sooner. The circuit also helps the output transition moreefficiently by recycling charge stored on internal nodes. These internalnodes and the output node switch logic states opposite to one another.Establishing a low resistance path between the internal node to theoutput node during part of the logic transition helps both the internalnode and the output node transition in the desired direction (from thecurrent logic state to the opposite logic state). Further, in particularimplementations set forth herein, the transition occurs withoutinitially pulling charge from the supply or sourcing charge to ground.

When the input node in is low the output node out is low. When intransitions high (a logic one), the pull-up booster becomes active.Transistor NI becomes transparent (conducting) creating a low resistancepath between the output node out to node nhi. This has at least twobeneficial effects. First, the output node moves toward a logic one froma logic zero, its desired direction, without pulling any charge from thesupply, V_(dd). Rather, the charge needed to transition the outputtoward a logic one is initially supplied by the charge stored on nodenhi (due to the capacitance, C_(nhi), of the devices connected to nodenhi). That is, the output node has a certain capacitance, C_(out), whichinitially is at a logic zero voltage potential. This capacitance has tobe charged when the output transitions to a logic one. When the outputnode out is tied to node nhi, these two capacitors act as a voltagedivider and the output node quickly reaches a voltage potential whichcan be expressed mathematically as:

V_(qs)=V_(nhi)*C_(nhi)/(C_(out)+C_(nhi)); where V_(nhi) is the voltagepotential on node nhi when the input is at a logic zero.

Thus, the voltage potential of the output node out is moved in the rightdirection without drawing any power from the supply which helps reducepower consumption.

Second, the node nhi moves toward a logic zero from a logic one, itsdesired direction, without sinking any charge to ground, GND, which alsohelps reduce power consumption. As node nhi moves toward a logic zero,transistor PU begins to conduct charge from V_(dd) to the output nodeout. PU continues to charge the output node, and its own gate throughtransistor NI, until node nhi reaches a threshold voltage below V_(dd)and PU ceases conducting. Accordingly, the initial charge to transitionthe output node out to a logic one is provided by the charge stored atnode nhi, while the remaining charge to complete the pull-up of theoutput node is provided by V_(dd) through transistor PU.

When in transitions from a logic zero to a logic one, the output of thesecond stage of the booster begins to move quickly after a single gatedelay (due to transistor NI). The output node potential quickly moves tothe potential V_(qs), which is determined by charge sharing when theoutput node is tied to node nhi as discussed above. The drive transistorPU moves the output node potential between V_(qs) andV_(thr)=V_(dd)−V_(pthr), where V_(pthr) is the gate to source voltage oftransistor PU that causes it to start conducting. The rate at which theoutput node moves between these two potentials decreases exponentiallyas it approaches V_(thr).

The pull-down booster operates when the output node out moves in theopposite direction, from a logic one toward a logic zero. When the inputnode in is high the output node out is high. When in transitions from alogic one to a logic zero, Pi becomes transparent (conducting) creatinga low resistance path between the output node out to node nlo. This alsohas two beneficial effects. First, the output node out moves from alogic one towards a logic zero, its desired direction, without sinkingany charge to GND. Second, the node nlo moves from a logic zero toward alogic one, its desired direction, without pulling any charge fromV_(dd). When node nlo moves toward a logic one, transistor ND begins toconduct charge from the output node to GND. Transistor ND continues todischarge the output node, and its own gate through PI, until node nloreaches a threshold voltage above GND and transistor ND ceasesconducting.

When in transitions from a logic one to a logic zero, the output of thesecond stage of the booster begins to move quickly after a single gatedelay (due to transistor PI). The output potential quickly moves to thepotential V_(qs), which is determined by charge sharing when the outputnode is tied to node nlo. The drive transistor ND moves the output nodepotential between V_(qs) and V_(thr)=GND+V_(nthr), where V_(nthr) is thegate to source voltage of transistor ND that causes it to startconducting. The rate at which the output node moves between these twopotentials decreases exponentially as it approaches V_(thr).

Generally, the latency of the booster circuit is improved by making thedrive transistors PU and ND large enough such that V_(qs) exceeds thethreshold voltage of the following stage. Because the potential V_(qs)is reached quickly, the next stage turns on sooner. This reduces latencyby starting the signal moving along earlier.

The full booster circuit depicted in FIG. 2 generally cannot function onits own because it does not drive the output node to full digital logiclevels. Other circuitry is generally required to restore the output nodeto full digital logic levels. For example, one embodiment of the presentinvention may use a keeper circuit (back-to-back inverters) at theoutput to restore the output voltage to the full rail voltages (V_(dd)and GND) during switching. Another embodiment of the present inventionmay use two series inverters operating in parallel with the boostercircuit (FIG. 3 discussed below). As previously discussed, a substantialportion of the charge used to change the output node potential isprovided by the booster amplifier. The charge needed to move the outputfrom V_(qs) to the supply may be provided by the second of the seriesinverters that is operating in parallel with the booster circuit. Aswill be explained below, the booster circuit and the two seriesinverters may operate more efficiently and with less latency than eitherthe booster circuit or the two series inverters acting alone.

FIG. 3 depicts a pull-up booster circuit operating in parallel with twoseries inverters, IN1 and transistors PZ and ND. When the input nodetransitions from a logic one to a logic zero, the two series invertersfunction normally and the pull-up booster circuit does not contribute tothe transition. The pull-up booster circuit however may contribute asmall amount of loading on the input node.

When the input node (Din) transitions from a logic zero to a logic one,after a single gate delay (the time for transistor NI to turn on),transistor NI becomes transparent, creating a low resistance pathbetween the output node Out and node nhi. Transistor ND remainsconducting (because it is conducting when the input is at a logic zeroand has not yet turned off) and further drives the gate of transistor PUdown beyond V_(qs). By the time transistor PZ begins to drive the outputto a logic one, the pull-up drive transistor PU has been pulling theoutput node to a logic one for a whole gate delay. As the potential onthe output node moves higher beyond V_(thr), the drive transistor PUturns off and transistor PZ finishes driving the output node Out to alogic one.

To determine the performance of the driver circuit depicted in FIG. 3,its performance was compared with conventional driver circuits that wereoptimally sized. The conventional driver circuits used two seriesinverters, three series inverters and four series inverters. For eachdriver configuration, a string of optimally sized drivers was used todrive similar loads. The first inverter was generally about the minimumsize as explained in more detail below. Further, the input capacitanceof each driver was about the same to provide similar step-ups. The inputcapacitance of each input device may generally be estimated by its gatecapacitance, C_(g), which may be mathematically represented as:

C_(g)=C_(permicron)*W=(ε_(ox)/t_(ox))*L*W; where L is the minimum gatelength for the fabrication process, W is the width of the gate, t_(ox)is the thickness of the gate oxide and ε_(ox) is the permittivity of thegate oxide.

Thus, the input capacitance may be specified using gate width when theminimum length of the transistors remain constant.

The minimum size of a standard CMOS inverter is generally determined bythe minimum length, L, and width, W, of a transistor gate (processdependent). Generally, the p-channel transistor gate is about two tothree times the width of the n-channel transistor gate to provide aboutthe same drive current for charging and discharging load capacitance toequalize rise and fall times. The p-channel transistor generally needsto be about two to three times the size of the n-channel transistorbecause the electrons used to conduct charge in n-channel devices aretow to three times more mobile, or conductive, than holes which are usedto conduct charge in p-channel devices.

For the string of drivers using two series inverters, as depicted inFIG. 4B, in each driver the two series inverters were optimally sized todrive the load given an initial driver size with an input capacitance of2 um. For the driver using a booster, as depicted in FIG. 4A, thetransistors PU and ND (see FIG. 3) were sized to have the same amount oftransistor width as the optimally sized second inverter of the twoseries inverters replaced. That is, for the driver using the boostercircuit, the sum of the transistor width used in IN1 and NI equaled 2um. PU and ND were matched to be the same size and p and n device in thesecond of the two series inverters. The booster circuit has extratransistor width equal to the sum of the widths of transistors PZ andPR. The size of the second inverter may be represented mathematicallyas:

Size 32 Size_(stage1)*SQRT (electrical gain); where electrical gain isthe capacitance of the load divided by the input capacitance of thefirst stage driver. For example, if the load is a size 10 inverter andthe first stage is a size 1 inverter, then the electrical gain is 10.This may be driven by two stages with the first stage being of size 1and the second stage being of size SQRT(10) which is about 3.1.

Further, the total transistor width (which determines input capacitance)contributed by transistors IN1 and NI was about the same size as thesize of the first inverter in the two series inverters being replaced.About three-fourths of this capacitance is contributed by inverter IN1and about one-fourth is contributed by transistor NI. Transistor PZ wassized to be about a fourth the size of transistor PU. Note that forminimum length devices, the sizing may be specified in terms of inputcapacitance, transistor width or drive strength which are equivalent.

The merit of the properly sized circuit depicted in FIG. 3 wasdetermined by modeling the circuit in Hspice, a commercially availablecircuit simulation program. The conventional driver circuits were alsomodeled using Hspice. FIG. 4 depicts the test setup for three drivercircuits modeled in Hspice. FIG. 4A depicts a string of three drivers,each having two series inverters with a pull-up booster, FIG. 4B depictsa second string of three drivers, each having two series inverters andFIG. 4C depicts a third string of three drivers, each having threeseries inverters. A fourth string of three drivers (not shown in FIG.4), each having four series inverters, was also simulated.

As depicted in FIG. 4, each driver in the string drives a load. Thisload is generally composed of the input capacitance of the next driverstage and a gate of a transistor sized so that the total load of thedriver results in a desired step-up. In FIGS. 4B and 4C, each of thedrivers is optimally sized for the given output load. For a totalstep-up of TS (defined as the output load capacitance, C_(L), divided bythe input capacitance, C_(in), of the inverter in the first driverstage), each driver in the chain has a step-up of about TS^(1/N), whereN is the number of drivers in the chain. The drivers of FIG. 4A, whichutilize boosters, were sized as described above. As previouslyindicated, each driver chain was designed to have about the same inputcapacitance and drives about the same output load capacitance. Thus,each driver chain has a similar step-up.

For example, if the size of the load is 18 um of transistor and theinput of the first stage is 2 um, the total step-up or electrical gainor G=load/input=(18 um+2 um)/2 um or 10. For FIG. 4B the first stage wassized to be 2 um and the second stage sized to be 2 um * 10̂(½)=2um*3.16=7.32 um. For FIG. 4C the first stage was sized to be 2 um andthe second stage to be of size 2 um*10̂(⅓)=2 um*2.15=4.3 um. It should benoted that 2 um *10̂( 3/3)=20 um=output load. For FIG. 4D the first stagesize was 2 um, the second stage to be of size=2 um*10̂(¼)=2 um*1.77=3.54um, the third stage to be of size=2 um* 10̂( 2/4)=2 um* 3.16=7.32 um, andthe fourth stage to be of size=2 um*10̂(¾)=2 um* 5.62=11.24. Again notethat 2 um*10̂( 4/4)=2 um*10=20 um=output load.

While FIG. 4 depicts circuits having a series of three drivers in eachchain, the simulation modeled the circuits as having a series of eightdrivers in each chain. The simulation measured the latency between thefifth and sixth drivers of each chain.

The results of the Hspice simulation are depicted graphically in FIGS. 5through 8 for a total step-up ranging from 1 to 140. At each step-up,the load capacitance driven by each driver chain was adjusted to achievethe desired total step-up. Recall that the total step-up of a chain ofinverters is the ratio of load capacitance to the input capacitance ofthe first inverter. The input capacitance of the first inverter in eachdriver chain was fixed at 2 um. Thus, the load capacitance at eachstep-up is 2 um * step-up (e.g., for a step-up of 50, the loadcapacitance on the final driver is 100 um). For each output load, thelatency between stages was measured and the amount of charge drawn fromthe supply was integrated over a complete cycle. FIG. 5 indicates thatfor the sizes chosen in the booster circuit, the booster circuit drivesthe output with less power consumption. FIG. 7 shows that even thoughthe booster circuit draws less power, it drives the output with lesslatency for step-ups less than about 80.

FIG. 5 depicts the total charge drawn from the supply in fempto-faradsfor each driver of FIG. 4 for one cycle versus electrical gain(step-up). As FIG. 5 shows, for the sizes chosen for the boostercircuit, the booster circuit drives the output with less powerconsumption (less loading on the supply) than any of the other driverconfigurations.

In addition to lower and latency, the area consumed on a chip might be aconcern. FIG. 6 depicts the total transistor width of the drivers ofFIG. 4 as a function of step-up. At each step-up, the transistor widthof each driver was sized to optimally drive the output load As FIG. 6depicts, the booster circuit contributes extra transistor width over thetwo stage driver but uses less transistor width that the three and fourstage drivers. That is, the area overhead for the booster circuit isusually insignificantly more that the two inverter driver design and isless than the three and four inverter driver designs.

FIG. 7 depicts the stage latency in picoseconds (vertical axis) of thedriver circuits of FIG. 4 as a function of total step-up (horizontalaxis). FIG. 8 depicts the latency of the drivers in picoseconds(vertical axis) over a broader range of total step-up (horizontal axis).As FIGS. 7 and 8 show, the two series inverter driver incurs less delaythan the three and four series inverter drivers for step-ups less thanabout 35. The three inverter driver incurs less delay than a fourinverter driver for step-ups less than about 160. The two seriesinverter driver with booster incurs less delay than two series invertersalone for all step-ups (the latency is about 10% less). The driver withbooster also incurs less delay than three series inverters for step-upsless than about 78 while using about 20% less power and about 15% lesstransistor width. The boosted driver also incurs less delay than thefour series inverters for step-ups less than about 125 while using about35% less power and transistor width.

FIG. 9 depicts the switching characteristics of an inverter with abooster circuit as compared to the switching characteristics of a normalinverter. Each inverter is driven by the same input signal and eachinverter drives about the same output load. The output of the inverterwith a booster reaches the 50% point (half the supply) faster than anormal inverter, but then tapers off after reaching about 950 mVrelative to a normal inverter. As FIG. 9 illustrates, the booster may beused to decrease latency along a logic path by decreasing the switchingtime of the logic to reach the 50% point at the expense of tending toskew the output signal (how long the output takes to reach the finalvalue). Thus, the booster circuit generally will not be able to passfrequencies as high as non-boosted inverters. This may be an acceptabletradeoff for circuits that may be having difficulty meeting timingconstraints but not pushing circuit bandwidth. An example application ofwhere such a booster may be beneficial is a trap handler. Such signalsoccur infrequently making circuit bandwidth less important than beingable to raise the trap handler flag as quickly as possible. Anotherapplication for booster circuits may be in a processor pipeline stagethat may be having difficulty meeting timing constraints.

The booster circuit may also be used to boost the performance of gatesthat implement logic functions. Depicted in FIG. 10 is a full-boostercircuit for the pull-up and pull-down portion of a two-input ANDfunction used by an embodiment of the present invention. Transistors PU,PR and NI act as a pull-up booster circuit for the AND function.Transistors ND, NR and PI act as a pull-down booster circuit for the ANDfunction. Transistors NJ, NI, PI and PJ perform the logic expressionevaluation of the AND function for the booster circuit. Recall that thebooster circuit also evaluates the same logic expression as the logicgate to which it is connected. Note that the booster circuit of FIG. 10would be connected to a two-input AND gate such that the in1 and in2terminals are connected to input 1 and input 2 of the AND gate and theout terminal is connected to the output of the AND gate.

The principles of operation the booster circuit shown in FIG. 10 aresimilar to the simple booster circuit described above. When both inputsbecome a logic one, a low resistance path is established between theoutput out and the gate of the transistor PU, node nhi. Charge sharingoccurs, bringing node nhi lower and causing transistor PU to conduct.Meanwhile, the output node out is initially pulled up due to chargesharing, and then pulled up to V_(dd)−V_(nthr) through the series NMOStransistors NJ and NI. The rest of the pull-up to a logic one isprovided by the AND gate to which the booster is attached. Acomplementary action occurs during pull-down except that when either in1or in2 is at a logic zero, a low resistance path between the node nloand the output node out is established.

FIG. 11 depicts the latency versus step-up for the boosted AND circuitof FIG. 9 and a non-boosted AND circuit. The latencies average risingand falling transitions for three cases: when a first input is changingand the second input is fixed at a logic one, when a second inputchanging and the first input is fixed at a logic one, and when bothinputs change simultaneously from a logic zero to a logic one.

FIG. 12 depicts an embodiment of the present invention for a full latchbooster. The full latch booster includes transistors PU, PR and NIacting as a pull-up booster and transistors ND, NR and PI acting as apull-down booster.

FIG. 13 depicts a simple latch booster having only a pull-up booster.Transistors PU, PR and NI form the pull-up operation. The rest of thebooster circuitry shown performs the evaluation function for a latch. Aspreviously indicated, the latch booster would be connected to a standardlatch such that the booster terminals Din, Q, ckt and ckf are connectedto the corresponding terminals of the latch.

The output, Q, of a latch copies the value at the input, Din, of thelatch when the clock, ckt, is a logic one. The latch booster reduces therising edge Din-Q delay and clk-Q delay. When the output Q changes to alogic one, it gets a boost. After a single gate delay after the secondof either Din or ckt transitions to a logic one, a low resistance pathis formed between the output Q and node nhi. This starts output node Qrising and node nhi lowering, the direction both nodes wish to go,through charge sharing. Then transistor PU begins conducting charge intooutput node Q. When node Q rises to within a threshold voltage ofV_(dd), PU ceases conducting and the traditional latch circuit takesover to finish driving Q to a full logic one.

It should be noted that there are many variables that contribute to theperformance of a booster circuit for a given step-up. The performance oflogic gates with booster circuits may vary depending on which input ofthe logic gate switches last and how much delay occurs between theinputs being switched. Thus, particular logic gates and/or logicfamilies may perform better with full booster circuits, pull-up boostersonly or pull-down boosters only.

Embodiments of the present invention may utilize full booster circuitsin parallel with logic gates to improve the latency of the logic gateswhile decreasing power consumption. Other embodiments may only employpull-up boosters or pull-down boosters to improve logic gateperformance. While the invention has been described using CMOS logiccircuits, this is by way of illustration only, and is not meant to belimiting.

1. A booster circuit for decreasing latency of a logic gate having aninput, an output and a nominal latency, the booster circuit comprising:an input node configured to receive a logic state transition; a firstswitch element configured to change to a conductive state in response tothe logic state transition; and a first node having a stored chargearranged to transfer the stored charge to an output node through thefirst switch element in response to the logic state transition, thetransfer of stored charge decreasing the nominal latency of the logicgate.
 2. The booster circuit of claim 1 further comprising: a secondswitch element configured to precharge the first node prior to the logicstate transition.
 3. The booster circuit of claim 2 further comprising:a third switch element configured to provide an additional charge to theoutput node during the logic state transition.
 4. The booster circuit ofclaim 3 wherein the booster circuit comprises a pull-up booster circuitthat assists the logic gate in a logic zero to a logic one transition onthe output.
 5. The booster circuit of claim 3 wherein the boostercircuit comprises a pull-down booster circuit that assists the logicgate in a logic one to a logic zero transition on the output.
 6. Thebooster circuit of claim 4 wherein the pull-up booster circuit reducesdynamic power consumption of the logic gate.
 7. The booster circuit ofclaim 5 wherein the pull-down booster circuit reduces dynamic powerconsumption of the logic gate.
 8. The booster circuit of claim 1 whereinthe first node switches logic states opposite of the output node.
 9. Thebooster circuit of claim 1 wherein the first node comprises a capacitiveload charged to a first voltage potential to provide the stored charge.10. The booster circuit of claim 4 wherein the logic gate comprises aCMOS logic gate.
 11. The booster circuit of claim 10 wherein: the thirdswitch element comprises a first p-channel transistor having a firstsource terminal coupled to a first supply voltage, a first drainterminal coupled to the output, and a first gate terminal; the secondswitch element comprises a second p-channel transistor having a secondgate terminal coupled to a second supply voltage, a second sourceterminal coupled to the first supply voltage, and a second drainterminal coupled to the first gate terminal; and the first switchelement comprises a first n-channel transistor having a third sourceterminal coupled to the output, a third gate terminal coupled to theinput, and a third drain terminal coupled to the first gate terminal.12. The booster circuit of claim 5 wherein the logic gate comprises aCMOS logic gate.
 13. The booster circuit of claim 12 wherein: the thirdswitch element comprises a first n-channel transistor having a firstsource terminal coupled to a first supply voltage, a first drainterminal coupled to the output node, and a first gate terminal; thesecond switch element comprises a second n-channel transistor having asecond gate terminal coupled to a second supply voltage, a second sourceterminal coupled to the first supply voltage, and a second drainterminal coupled to the first gate terminal; and the first switchelement comprises a first p-channel transistor having a third sourceterminal coupled to the output node, a third gate terminal coupled tothe input node, and a third drain terminal coupled to the first gateterminal.
 14. The booster circuit of claim 1 wherein the nominal latencyis measured at a 50% logic state transition point.
 15. A method forreducing latency of a logic gate having an input node, an output nodeand a nominal latency, the method comprising: coupling a booster circuitfrom the input node to the output node, the booster circuit providing atleast one charge sharing mechanism between at least one internal nodeand the output node; receiving a logic state transition on the inputnode; transferring a charge from the charge sharing mechanism to theoutput node in response to the logic state transition; and decreasingthe nominal latency of the logic gate through the charge shared.
 16. Themethod of claim 15 wherein the booster circuit comprises a pull-upbooster circuit that assists on a logic zero to a logic one transitionon the output node.
 17. The method of claim 15 wherein the boostercircuit comprises a pull-down booster circuit that assists on a logicone to logic zero transition on the output node.
 18. The method of claim15 wherein the nominal latency is measured at a 50% logic statetransition point.
 19. The method of claim 15 further comprisingactivating a switching element in response to the transfer of charge tofurther charge the output node.